1. Field of the Invention
The present invention relates to a method for fabricating a flash memory device and, more particularly, to a flash memory device whose characteristics are improved by increasing efficiency of hot electron injection via changing a conduction band energy level of a tunnel oxide layer.
2. Background of the Related Art
FIG. 1a shows a conventional floating gate device. The conventional floating gate device can be fabricated as follows. First, SiO2 1 as a tunnel oxide layer is grown on a P-type silicon substrate. Then, a polysilicon floating gate 2 is deposited on the tunnel oxide layer. Next, an ONO (Oxide-Nitride-Oxide) layer 3 is deposited on the polysilicon floating gate in most cases to increase a coupling ratio. Thereafter, a gate is made by forming and patterning a control gate 4. Finally, a source/drain impurity region 5 is formed in the silicon substrate by performing an ion implantation process using the gate as a mask.
FIG. 1b illustrates an energy band diagram of the conventional floating gate device. In the floating gate device, a ‘program’ operation increases a threshold voltage by confining electrons in a potential well formed between the floating gate, the tunnel oxide layer, and the ONO layer by hot electron injection. On the contrary, an ‘erase’ operation decreases the threshold voltage by transferring the electrons confined in the potential well to the P-type silicon substrate by direct tunneling or F/N (Fowler-Nordheim) tunneling. Such a floating gate device has very fast program speed, good retention characteristics, and a wide threshold voltage window. Therefore, floating gate devices are now employed for most commercial non-volatile memories.
However, for a floating gate device using SiO2 as a tunnel oxide layer, the efficiency of hot electron injection is relatively low due to a high potential barrier of 3.5 eV formed between the tunnel oxide layer and the P-type substrate. In addition, high energy of an electron sufficient for jumping the potential barrier is completely lost while injecting the electron into the potential well formed in the floating gate. The energy loss generates a trap on the interface of the tunnel oxide layer, thereby changing the threshold voltage of the floating gate device. Consequently, frequent operations of a read and a write cause degradation of characteristics of the floating gate device. Moreover, thickness of the tunnel oxide layer should be about 80 to 100 Å to guarantee retention characteristics. During an erase operation, as the tunneling length of an electron is very long in the tunnel oxide layer, an erase voltage is so high and an erase time is so long that an erase characteristic becomes poor.
Korean Published Patent No. 2003-50999, Park, discloses a flash memory device enhancing characteristics of a program and erase operations by enlarging the contact region between the floating gate and the control gate. Further, U.S. Pat. No. 6,456,535, Forbes et al., and U.S. Pat. No. 6,384,448, Forbes, disclose methods for enhancing program characteristics by increasing hot electron injection via depositing a very thin tunnel oxide layer of thickness of less than 50 Å. However, the thinner the thickness of the tunnel oxide layer is, the poorer the retention characteristics are.